Good day, Ashish Ranjan Shadangi. I'm Arjun. I've had a look through your background and your professional record. I'm interested in hearing more about your work and how you see yourself fitting in here with our faculty. Ready to start?

Yeah.

Good morning, Sir.

I'm assistant and certainly.

So I completed my B.Tech from Vignan Institute of Technology and Management with them from Bharampur. It's under BPUT Biju Patnaik university for technology.

I'm from Barampur, Odisha.

And Mtech also I did under BPUT university only and PhD I completed recently in last year 2025 and I got awarded in July. However I submitted my VHD thesis.

December of 2020 fourth. So I completed my PhD from IIT Kharagpur Sir.

Yes.

Thank you for the clarification, Professor. Let us now discuss your experience and skills in more detail. Starting with your teaching approach, how do you ensure that both theory and laboratory courses are engaging and effectively understood by students?

Yeah, thank you for asking these questions, Sir. Actually like as I told uh, in 2024 December, I submitted my thesis at IIT Kharagpur, then after I joined in one of the autonomous college here at KPR, IET Coimbatore.

So from since 2025 January till.

This time I'm working here as an assistant professor. So, uh, like, as you asked, like, uh, how my teaching ability will help. So here for last two semesters, they have been assigned me many subject subjects like our core subject, digital electronics and, uh, design for testability.

And electronic device and circuits. So these are the core subjects that I handled however like as far as.

Lab approach. So some of these subjects were layer learning subject. As you know layer learning subject means with theory.

And lab both are there so like digital electronics if I will go to digital electronics there digital electronics theory subject anyway I was teaching in class. However for that laboratory also was there. So there you can find multiple number of lab experiments like.

Basic, uh, get how to utilize basic get operations, then uh, halfway the full ladder.

And then sequential circuit, if you will go, it's coming under suppose Sr. flip flop, D flip flop, JK flip flop, even counter also and registers. These are certain numbers of experiments that was there in digital electronics. And again, so that time many kids are there so we can use directly those kit and we can use the IC of end gate or get exergate everything so.

We can use to design the sequential circuits because mostly the combinational circuits only used to design the sequential circuits. Most probably. However, the difference between combinational and sequential circuits is only clock clock differentiation. So in combinational circuits there is no clock. However, in your sequential circuits there is clock. So these are certain numbers of experiments. I was doing.

In our laboratory class for digital electronics and as far as my research area, most of the time like during my PhD, my core was in VLSI, very large scale integration. So there I used to design architecture for 6G communications like you might have known Otfs, orthogonal time frequency space. So in 6G they are targeting for high-speed vehicular communication. So it's VLSI architecture. I work upon during my PhD, so it's direct.

Actually related with the VLSI and that's directly related with the digital electronics. So digital electronics it's like.

Hand in hand kind of subject for me because it's directly related to my.

PhD work that is in VLSI set and my research related application is mobile communications. So high-speed vehicular communication means 6G mobile communication. But its core part VLSI I targeted and digital electronics is directly related to VLSI. Thank you.

Thank you for the detailed explanation, Professor. It's evident that your approach weaves together both theoretical instruction and practical application, especially in digital electronics. Your integration of hands-on laboratory experiments with foundational concepts, like combinational and sequential circuits, is commendable, as it bridges the gap between theory and application effectively. Given this approach, can you explain how you assess student understanding during your courses, both in theory and in laboratory settings? Specifically, what strategies or methods do you use for evaluation?

Yeah, thank you for asking this question, Sir. And like as you know, whatever we are reading, suppose, suppose theory subject we are reading if we can implement those in our practical.

Physical environment then students can closely relate that theory but whatever they studied and they can see kind of they can visualize also right Sir? So digital electronics that I told.

So theory part edge you know syllabus is there for combination first. First of all number systems first of all we have to know the number systems like binary, octal, hexadecimal, decimal. So these are the number system. Number systems are the basic. On top of that we are using this number system to design any circuits as well also. So now. The number system is one of the topic for the digital electronics then coming to combinational circuit sequential circuits. So as per.

Your question how exactly I'm approaching towards the laboratory like let's check. So that's why how I am approaching like full adder and half adder. Suppose pool adder maximum 2 bit inputs it's taking and some and carry it's giving same way full adder it's taking 3 bit input and we are getting some and carry. But now how to visualize so that visualization we can do by pract.

Wait now as we know how better some, some, some and carry are the two outputs. So some equals to a exer B and.

Uh, carry equals 2.

A and with B.

So like here a excerpt B we have exert IC.

So inside one excerpt I see there are 4 exer gates are there. But anyway we need maximum 2 exergate because one exergate right? So because some of half adder equals to A, X or B. So inside that IC4 exergates are there. And as you know each IC have multiple pin numbers so based on input pin 12 pin are input.

And three pin is your output. So if you will give input so we can give input by using that key again with that switches it will switch switch on that will be 1, if it will be off that will be 0. That way we can give the inputs to that pin number one and two of XOR IC to get output from pin number three that is some output same way. Carry output Carry inputs also 2.

And B so we have to give either pin number four and five input and output we will take from six. And to work this IC pin number 7th is your ground and VDD supply is at your pin number 14. So that also we have to take care that IC we have to place on the breadboard and we have to connect A&B by using pin number.

One and two so and switches will be the inputs. So this is what small scenario. Now coming to full adder. Suppose we will do then full adder anyway 3 inputs are there ABC same way we can use one more instead of 1. Exergate IC will be only one because inside one IC there are 4 exergates but out of that four for full adder. Some find out, find out we will use two.

From that Excel IC, so this is the, uh in class we are teaching like uh, summation equals to uh, some, some of the full adder equals to H or B and uh, your.

Carry output equals to A multiplied with B. But how exactly you will visualize like a student will visualize by doing practical implementation. So this is how the small circuits we can design by using Brad board and even by using IC so that they can implement by themselves. Student have to understand by themselves. So this is small example. Later point of time you can design combinations, sequential circuits, counter you can.

Like counter also suppose.

Uh, three bit counter. So 3 bit counter means, uh, it will maximum count from zero up to seven like 000001 like that it will suppose up counter it's count kind of kind of up counter 0123 up to seven if it is down counter 73 bit down counter 76543210. So this way anyway, group table you will use which a particular flip flop you have.

2 table excitation table. From there you designed but on board breadboard you have to use and gets and I see by using this even flip flops. Also you can implement and you can give it clock and based on your architecture you will give the inputs. Finally you will get the output. So this is the way students can visualize. So it's directly related to like visualization of theory by implementing.

Too huge to find out this your counter to to design counter. So suppose Sr. flip flop or D or D any flip flop. So it's having its own your.

On breadboard handsome session so you will get more clarity. So that approach I follows first student to get visualization of the theory concepts. Thank you.

Thank you for the detailed explanation, Professor. It is clear that you take a meticulous approach to integrate theoretical understanding with hands-on practical application. Your emphasis on visualization and the use of breadboards, ICs, and circuit design provides students an effective way to bridge their conceptual knowledge with real-world implementation. Now, let us discuss your research contributions. Can you share how your VLSI research, particularly in the context of 6G communication, has been published or recognized within academic or industry circles?

Yeah. Thank you. Thank you, Sir. Thank you for asking these questions like.

I joined my PhD program in 2019 July month and I submitted my thesis in December 2024. So it's took around 5 and half years. So I enjoyed that PhD tenure because every day I used to get many things. I was learning many things. So in which way I was learning like.

With senior interaction and even with the supervisors interactions, I used to note down many points. Now I will come to your point like you asked how exactly what exactly my research was right. So if I will tell like you see in 4G and 5G OFDM technology was used. As you know OFDM, it stands, it stands for orthogonal frequency division multiplexing. But now. You might have seen like suppose we are. Uh, going with the 4G or 5G handset mobile, uh, we are sitting in train and train is moving at Max 100 kilometer per hour. At Max, I'm telling it will go up to 70 kilometers per hour or 80 kilometers per hour. But you might have faced it this problem like suppose you are connecting, uh, uh, to your friend or relative in sitting inside your train and the train is moving 100 kilometers per hour. Suppose, but you might have faced some connection disconnect. Connection you are facing right connectivity problem but that is what happening in 4G and 5G handset. So to get connect connection you have to still in particular position and your vehicle movement should not be that high speed. But for 6G communication people are targeting for high speed vehicular communication like bullet train. Suppose tomorrow you will sit with your 4G or 5G handset inside a bullet train. Think about bullet train is moving.

Speed right So more than 200 kilometer per hour, 300 kilometer per hour. So there how you will get connect connection you cannot get connection but 6G is targeting for high speed regular communication like suppose a vehicle is moving with high speed still.

Right. So that way, uh, this 4G and 5-GO FDM technology is not working at all for high speed vehicular communication. That's why people have proposed OTFS, orthogonal time frequency space modulation scheme. So even if a vehicle is moving with high speed, high vehicular, high speed, uh, high speed still connection should not get lost. Now why how what exactly they are doing? They are doing like.

It will uh, this connection should not get lost.

They're considering our signal. In delayed OPERA domain instead of time frequency domain like in OFDM time frequency domain signal even channel were also considered for time frequency domain. But now for OFDM for Otfs they are targeting for delayed Doppler domain. Why for a particular time and particular frequency one particular delay is always fixed based on you can see multiple documents from three GPP, multiple documents they have. Based on that we can.

The data now this way many different blocks are there, like ISFT inverse symplectic finite Fourier transform, Heisenberg transform. I'm telling transmitter side blocks, Isfft inverse symplectic finite Fourier transform, then Heisenberg transform, then signal is transmitted from the transmitting antenna at the receiver. From the receiving end receiver and receiver front end will catch that signal, then again reverse.

Will happen Wagner transform, SFFT, symplectic finite Fourier transform. So this way we are encoding from the transmitter side, we are decoding from the receiver and and even channel estimation, channel equalization. So then simple detection and bitstream generation then finally digital to analog conversion. So this is what happening in exactly in digital signal processing way. Now coming to my part like. This DSP digital signal processing happening.

By considering some metrics right? So matrix means there will be matrix multiplication matrix, inversion matrix.

Complex conjugate transpose that is Hermitian, so multiple equations are there. My part for PhD program I designed architecture for Otfs both for transmitter and receiver for different channel, a double GN channel, additive white Gaussian noise channel and multipath fading channel.

Uh, but both channel I designed now, uh, how I designed like as we know, uh, VLSI side is mostly focusing on three most important area that is area power and latency. These three we have to keep.

Keep eye on these three perspective. So you can write a big equations but that equation if we will implement on FPGA board.

Then FPGA board will take too much power, but power is one of the concern for VLSI area. So that's why we have to optimize our architecture. We will implement that equation but we will optimize our architecture in such a way with less resource utilization. I can implement that same equation by on FPGA board or maybe tomorrow we will come up with some cheap. So like that multiple equations are there in Otfs.

People have proposed algorithms like my seniors under my supervisor, he proposed. So those 3 algorithms I implemented and I checked how much resource utilization, how much power it's it's consuming, how much time it's taking to give the that output. So I went up to structural level and as I studied edit subject architectural design for integrated circuit during my PhD coursework at Karakur, so.

There our professor taught how we can optimize a particular circuits like if we will reduce the bit width of a particular parameter and if we will multiply the Suppose multiplication A into B but A is of two width OF10B is of width of 10. Then if we will multiply A into B then your resultant output with Y equals to 20 bits right Sir So that time. Now is that Pontius really needed or is that 10 bit for A and 10 bit for B? Is it really needed if we will shorten to 6, speed up a six bit of B, Can this be accommodable? If we can reduce our width, width our power and partial products will be very less. By that way we can use less resource and less power to get the particular output. So this. Basic building level if we will optimize adder multiplier subtractor. Even in person and even cordic architecture, you might have seen sin Theta, Cos Theta find out. So if we will optimize this way, small, small basic building block, if we optimize and that we will implement into our particular equations. Equations are nothing but combination of small, small basic building blocks. That's it. So it will optimize in basic building level that what exactly I did and. That way we can reduce the resource utilization, power utilization and we can do.

Sorry

I mean analysis. So this way I designed my architecture during my PhD program. So this is how my research was going on. So I enjoyed my research program during PhD Thank you.

Thank you, Professor, for that extensive overview of your research work. It’s impressive how thoroughly you approached the design and optimization of VLSI architectures for OTFS modulation and targeted critical challenges like reducing power consumption and resource utilization while maintaining performance for high-speed vehicular communications. Your detailed work with metrics, FPGA implementation, and optimization at the building block level highlights both your technical expertise and depth of research. Let’s turn to another aspect of your contribution. Could you elaborate on how you guide students in their projects or research, especially considering your rich experience in VLSI and digital electronics? How do you mentor them through complex technical areas?

Yeah, thank you. It's a nice question. Like as during like from January 2025, I have been working here in Coimbatore. So multiple projects people are doing, like I have been assigned 2 teams, like 2 teams, each team contains 3, three students, so total six students they were undergoing.

In.

Mind supervision. So what exactly they have done Like one team they have designed.

Small FFT like first Fourier transform because it's a basic building block. How it will help see everywhere in digital signal processing. FFT, IFFT, Finite Fast Fourier Transform, Inverse Fast Fourier Transform are the basic building blocks. So we can optimize those FPT even although it's reached to the.

Top level optimization. Now FFT is fully optimized, but just for sake of to get the practical implementation to start with a B.Tech project 1 Btech student can design FFT. So in out of two team, one team they designed FFT with, they have to know what exactly happening like you can you also know like butterfly structures are there how those?

Wait, see who you are defining how those weights are going to multiply with the particular sample and how that suppose three stage butterfly stages. So each stages will give definitely some output by multiplying, adding some weight with your samples and all. So then finally you are designing this way that team designed FFT and they have implemented by using very low code and finally they implemented on FPGA board. So this is 1 approach I assigned them to allow them to visualize what exactly happening. Second team they designed some fire detection by using your your adeno board how any firing fire happens. Any plane comes how it will detect exactly on the time, how everything will be shielded, so that others should not be disturbed so.

By using adeno board they have designed and we know adeno board have two stages set up and.

Your loop. So by that way I allowed them, I assigned them some work and they designed some of the hardware like prototype kind of.

Thank you.

Thank you for sharing that, Professor. It’s evident that your mentoring approach is hands-on and allows students to engage with foundational and practical projects that help them grasp complex technical concepts. Your focus on guiding them through critical building blocks like FFT and enabling real-world applications, such as fire detection using hardware, highlights your clear ability to inspire and guide students effectively. Let’s now touch upon another area. Could you explain how you manage exam-related duties, particularly in terms of evaluating students fairly and ensuring the integrity of assessments? How do you typically structure exams to comprehensively assess both theoretical and practical understanding?

Our scheduled time for the interview is now up. Before we conclude, do you have any questions related to the role or the company?

Ah, yes, thank you for asking this question. I will simply touch on to that exam related like a year. Also they are assigning some duration like during exam duty they give exam duty anyway exam duty like we are going as an invigilator where distributing paper, collecting paper where keep eye on any if anyone, any students because students are still students. So students they are. They definitely will cheat but.

So we, we have to inspect them and we have to, uh, guide them. We have to mentor them kind of. So we have to see whether continuously whether they are doing any cheating and so malpractice. That's, that's a separate thing. But now as far as you asked how I am evaluating, so evaluation duty also, they have been assigned me last semester also. So like, uh, see students, uh, they, they are learning. So the learning should be given most priority.

So we should not restrict marks. We can, we should somehow literally we have to give marks liberal way because they are learning if they will get some marks, they will get enthusiasm, they will get enthusiastic to learn even more, right. So, so some students, those who are not really focusing on study then for them we will give some less marks to so that they will do better in next step. But those who are really putting their efforts, they should get.

Whether the student is approaching towards the particular way which can lead him or her to get the final output, whether they're getting output or not, that's different thing. But stepwise whether they're going in correct way because once they will get long then definitely they will excel in that particular subject and even they can do better also. So I am approaching, I am during evaluation I mostly focus on. How they're approaching based on your based on their approach. I I'm sending some marks, suppose 5 marks question is there answer is not correct, but the steps are very good and the perfect way here she is going then better to give her 22 and half three marks or four months. So that later point of time they will ask Sir what exactly happened. We can explain see this is how the way you went. I really appreciated your steps, but how you are you can do good means you have to focus more on exact focus how you will get that particular. Outputs so that way we can, uh, tell them student this way you followed is fine. But now onwards you focus on how exact output you will get out of your, uh, final step. So this is the way I am approaching for evaluating a particular students. Thank you for asking this question and final question like, uh, you asked me like what uh, extra question I have to ask. There is no as such.

Awarded so, uh, based on, uh, students, uh, effort and by seeing, uh, those answers kept step by step, uh, approach if they are going, whether they're not getting the exact answer output, but step by step, even in digital electronics. Also, if you are going with the one, umm, UH-1 level to other label, uh, one step to other step, you can see how they are approaching towards a particular problem. So you should. For me, I'm thinking.

Extra question, but if you can.

Tell me. Like what kind of role I will be given in university? Like anyway some associate professor, full professors, even assistant professors, Many steps are there and how I can add my expertise in your institution. If you can guide me and I can improve myself and whatever I told if you will guide me what improvement needed from my side so that I can.

Really add value to our VAT university? Please tell me.

Thank you for your thoughtful remarks, Professor. Based on the role outlined by our institution, you would be contributing as a faculty member in areas that align strongly with your expertise, potentially as an Assistant or Associate Professor depending on the institutional requirements and your experience. Your responsibilities would span key domains such as: - Teaching both theory and laboratory courses, particularly in areas like digital electronics and VLSI. - Guiding undergraduate and postgraduate research, much like your mentorship of student teams currently. - Evaluating students effectively, ensuring clarity in both practical and theoretical comprehension. - Publishing impactful research in international journals, an area where you already hold significant experience. - Contributing to institutional research and consultancy efforts, particularly in advancing embedded and communication systems or other relevant technologies. Regarding improvement, one area that may strengthen your profile further is a focus on collaborative industry research or securing funding for high-value projects. Universities increasingly value faculty who can bridge the gap between academia and industry. Additionally, if you are involved in activities like institutional accreditation or curriculum design, it would add to your portfolio significantly. Your current expertise in VLSI, digital electronics, and student mentorship is impressive, and adding these dimensions could further elevate your contribution. Let me know if you'd like additional clarification or specific advice.

Yeah, I think.

Time is