Good day, Dr. Pritesh Kumar Yadav. I'm Arjun. I've had a look through your background and your professional record. I'm interested in hearing more about your work and how you see yourself fitting in here with our faculty. Ready to start?

Kumar Yadav Right now I'm working in BITS planning Hyderabad campus as a Visiting Assistant Professor. I joined here in.

February 2024. Since then I'm working here so I've taken the various courses like RF Microelectronics.

Analog electronics, Microelectronic. The field that is, that is related to the circuits and the.

High frequency circuit that is basically out of my electronics which is my basic core area and previously I have worked on the IIT Kanpur as a project scientist in which I have worked on the design and development of a 79 number.

17 micrometer RYCRYC is basically the readout integrated circuit.

In which basic they have set up the asset design from the RTL to GDS 2 flow in TSMC 139 motor technology.

And design A stochastic amplifier from till the specification till the post layout simulations and done the tape out of a 28 MMM square chip using TSM 3113 and motor technology. And previously I completed my PhD from Triplet Allahabad in 2022 where I worked on the design design of the receiver front in architectures with improved performance for. Among way, but applications in which basically are targeted to increase the.

Linearity of the overall receiver chain because the researchers basically previously, we have found in the literature that researchers basically uh.

Performance parameter that is either maybe linearity or the gain or maybe the noise figure. But our target is to improve the overall performance of our receiver front end chain that includes the the receiver front entity and basically includes the LNA receiver and the followed by the IF filter. And this mixer will basically down convert the RF equals into the frequency with the LO that is the local oscillator.

But working on particular.

So my target is to improve in this in my PRD, my target is to improve the linearity of the older receiver. And that is why I have incorporated the linearity improvement techniques in the last stage of the receiver chain that is the IF filter stage. So because the last stage that is basically dominant for the overall linearity of the receiver chain and.

Finally, if my linearity of the reservation will be improved, then the overall performance that will be evaluated by the figure of merit term that is directly proportional to the conversion gain noise figure and linear.

Sorry, that is uh, that your question with the conversion gain linearity and the operating frequency and inverse portion of the noise figure and the power dissipation and the in this in order to evaluate the figure of merit term, the linearity will basically the most dominant performance parameter. So that is why I have basically improved the linearity the overall receiver chain. Then I have incorporated this into the evaluation of the figure of maritime so that the overall performance has been improved.

And basically I've designed 3 architectures in order to improve the this overall performance that has been designed using the UMC 40 nanometer technology and the.

130 nanometer by CMOS technology.

And previously have completed my M tech in 2017 with the CGP of 9.15 where I worked on the design and verification of a five stage pipeline. This CPU using 180 nanometer CMOS technology and.

Uh, this I've also done from the RTL to GDS 2 flow in order to complete the Essex design. And previously I completed my B.Tech in 2014 from Uttar Pradesh Technical University with the percentage of 72.90. And I've worked on uh, basically a MATLAB coding in.

In the In the final year project.

So basically I fit in VITS so that I will basically design A, uh, basically, uh, renovate a lab related to the RF and the analog ISIS actually, because I have worked on the tip out. That is basically the major area right right now. And the industry basically demands that, uh, the analog circuit design or the RF circuit design are based or maybe the digital design. So basically I have, uh, design and develop a lab related to the RF microelectronics or.

With the that is basically focus on the tape outs so that.

That is the how I will fit in the into the VIP.

Thank you for sharing your academic and professional journey, Professor Yadav. I appreciate the detailed overview of your experience and research work. Let us move forward.

Yes.

Let's begin by verifying the key skills critical to the Professor role. I'll ask you targeted questions to assess your expertise in these areas. First, can you describe your practical experience and depth of understanding in image processing? Specifically, have you applied image processing in any significant projects or research?

I have my base core area is basically related to the RF analog IC circuits, but I have basically worked on the image processing in the last year five year project of the B.Tech where I have.

Encrypted data into the image so that it can be decoded by the other one sent to other.

Incorporated the.

Uh other person so that they can decode it by using the image only so it will it will be encrypted.

But my core area is basically on the RF high frequency circuit, so I have not basically my target. My core area is in the image processing.

I'm not too much work in my M tech and the PhD regarding this.

I told you my core area is related to the analog in other circuits. My domain is not related to the embedded and the communication.

Understood, Professor Yadav. It seems your exposure in image processing is limited to your earlier work during your B.Tech, primarily focused on encryption embedded within images. Your core expertise aligns more closely with RF and high-frequency circuits. Let’s move to the next skill. Can you elaborate on your knowledge and experience in embedded systems and communication, particularly in designing or implementing such systems?

Noted, Professor Yadav. Since your core expertise lies in analog and RF circuits, we’ll keep to your domain strengths as we proceed. Moving on, how have you contributed to teaching, specifically in leading both theory and laboratory courses? Could you share an example of a course you taught or helped design?

Yeah, I right now working in the Batsman Hyderabad campus. So in the last semester I've taken the RF microelectronics for the higher degree course. So I basically my target is 2 because the student nowadays getting bored when we are just doing the teaching. So that is why I've incorporated A1 lab so that if I will discuss one of the topic, then the same thing can be implemented in the lab use using the KN for QSO 2 so that suppose if I'm.

Basically I will discuss the procedure, how to design this. So same thing we can add in the lab so that they can implement the same thing using the Cadence virtual support, using multi nanometer technology so that they can be more interested towards the.

Thought if I taught the element design using this source degenerate cache code topology uh by.

This particular any of the.

Courses or any of the topic technical thing that is.

That's an excellent approach, Professor Yadav. Incorporating hands-on labs alongside theoretical instruction is highly effective, particularly when using industry-standard tools like Cadence Virtuoso. It not only engages students but also bridges the gap between theory and practical application. Now, regarding student evaluation and exams, could you share how you've assessed student learning outcomes in your courses? For instance, what methods or strategies have you used for evaluating their performance?

Sorry, can you please repeat the question?

Certainly, Professor Yadav. Could you explain how you assess student learning outcomes in your courses? For example, what methods or strategies do you use to evaluate their performance effectively?

So basically I've incorporated one of the basically in the wholesome stuff, incorporated 3 to 4 surprise quizzes so that I can get the idea that how the student will perform and do.

33 surprise users will be there. So accordingly I can get an idea if anyone is to any student will not perform good then I will basically focus on that one particular student and I discuss personally then what is their problem and how they are not able to score good and if they have some problem and then I can discuss with them personally.

Maybe in the whole semester, within after maybe within a month, I will take one quiz and there are.

And from that I get the idea that how the student will perform if and they can also present present theirself in my cabin so that I so they so that they can know better about the project. And if I will given the task 1 by 1, I will not give the whole thing at a time so that the student will be confused. So once I will discuss the discuss what is the progress in the weekly meeting, then I will give the another task so that they can perform in the whole particular week. And again, we will meet regularly in the.

That's a thoughtful strategy, Professor Yadav. Regular surprise quizzes not only keep students engaged but also help identify those who may need additional support. Taking the initiative to personally address their challenges reflects a strong commitment to student success. Moving now to guiding student projects and research—can you provide an example where you supervised a student project or research and how you supported them throughout the process?

So basically I'm taking the weekly meetings so that student I will.

Take I will take the weekly meetings for the projects.

Like this?

Your structured approach to guiding student projects is commendable, Professor Yadav. Weekly meetings and breaking tasks into manageable steps not only prevent confusion but also enable steady progress and learning. This method demonstrates strong mentorship and project oversight. Let us now discuss your teaching methodology. How do you ensure clear communication and a structured teaching approach during your lectures or labs?

So basically I've prepared the lecture slides so that because I want to share whatever I've discussed so. But basically the slides will be just there to.

Tell the student this is our topics and what are the what has been discussed. But basically I have my approach is to write each and everything in the whiteboard so that I because if I will start from the beginning that how the circuit has been designed and how it is actually been implemented and how the whole derivation will be whole mathematical calculation will be there, how we'll get the gain and the noise figure and the other things. So that they can get a more better idea and.

Then I will provide the slides with them so that they can just revise the whole thing and they can understand better.

Your methodology demonstrates a strong commitment to effective communication and clarity, Professor Yadav. Using the whiteboard for in-depth explanations followed by providing slides for revision creates a balanced approach that caters to deep understanding and retention. It reflects a thorough and student-centered teaching strategy. Next, I’d like to discuss your academic qualifications. You're a Ph.D. holder—could you briefly share your area of specialization and its focus during your doctoral research?

Yeah, I've already discussed a few things initially, but my PhD is basically on the RF microelectronic sites in which I have worked on the design and design of a receiver front end architectures with improved performance for MMM waveband applications in this particular, in this, in this particular area, I have worked on the improvement of the linearity, linearity of the overall receiver change that incorporates the. LNA mixer and followed by the if filter stage.

So basically I've worked on the LNA mixer as well as the I filter say and hello. I have taken as an ideal source. So I have designed this for a 20 gigahertz frequency band. So a single stage of LNA is not sufficient to provide the sufficient gain for this particular higher frequency. So that is why I have incorporated 3 stage alna where the first stage is basically dominated for the better noise figure because the noise figure is dominant by the first stage only of the whole issue of content chain according to the first equation then.

Design for a better game. At first stage that will convert the single ended signal into a differential ended because the next thing that is the mixer that is needed the differential and signal and also the differential Android signal differential and amplifier that will improve the linearity and it followed by the mixer that will down convert the RF frequency of 28 gigas into the one gigahertz frequency. Then finally if filter stage will be there that will basically remove the unwanted frequency signals. So finally we have the channel.

The second stage of the LNA will be.

So where I, uh, which I've designed basically I've designed 3 architecture to do that. First two design has been designed using the UMC 14 nanometer technology in the Cadence ratio 2 and the law. And the third one is designed using the 1:30 nanometer by CMOS technology using the Cadence virtual tool. Only the finally, if I will able to improve the linearity in the last stage of the receiver change, then I will be able to improve the overall linearity of the receiver chain because the linearity is basically dominant in the.

Channel channel frequency after the higher frequency. So I have incorporated the linearity improvement techniques in the if filter stage basically.

Last, the other is with any system, so that is why if then finally, the overall performance has been evaluated by the figure of merit term that is directly proportional to the conversion game, directly proportional to directly proportional to the linearity, directly proportional to the operating frequency, that is 20 gigahertz, and inversely proportional to the power consumption and inversely proportional to the noise figure.

So finally, and in the in the evaluation of the overall figure of many term, so that is basically, uh, dominant by the linearity mostly. So that is the if I will be able to improve the linear to my overall receive of front end chain has been improved. So in the previous literature, the researchers basically, uh, basically focus on one particular performance parameter by, but my focus is to improve the overall receiver front end overall performance of a receiver front tension, that is by how.

Plan these things into my PhD thesis that is a brief description of my.

Thank you for the detailed explanation, Professor Yadav. Your Ph.D. research demonstrates an impressive depth of expertise in RF microelectronics, particularly in the design and optimization of receiver front end architectures for mmWaveband applications. Your focus on improving linearity while balancing other key parameters like gain, noise figure, and power consumption reflects a comprehensive and innovative approach to addressing challenges in high-frequency circuit design. Let’s now move to research publications. Could you highlight some of your key publications, particularly in reputed journals, and the main contributions or findings of those works?

So in I basically published 4 journals and three right now in the under under review mode.

So in the four submission, in the first submission I basically design active inductor.

For five gigahertz uh, wireless man. So basically, but the the problem is that when we are designing a receive a front end chain. So basically the LNA has been designed with the inductors. So the inductor basically consume more than 90% of the area. So that is why my target is to replace this passive inductor with the active inductor. So I have designed the active inductor for A5 gigahertz wireless line that will be.

Uh, act as an application for a?

I feel the same. So the same thing I've incorporated into the receiver content change because the first thing that is the alignment that will then it is followed by a mixer then will down convert it to lower down number to the channel frequency that is 1 gigahertz. Then I will the mixer is normally it is having the only R load, but I have replaced this R load with the RLC load. So and in the RLC load the L that will be needed that is in the microhanded range so that is not.

Uh, filter.

Able to integrate on chip. So that is why I've replaced this passive inductor with the active inductor. This is one of the paper that has been published and the second one. Basically I've incorporated the linearity improvement techniques of the resistive source degeneration and the cross coupled pore distortion technique. So basically the cross coupled core distortion technique will basically provide the negative GM 3.

Sorry, the will basically reduce the effective GMC component of the differential pair so that the effective GM three of the differential way that will be decreased so that the overall.

Linearity has been improved because the linearity is mainly dominant on the GMT company and the other technique that is the residual degeneration technique that is act as a negative feedback so that the linearity has also been improved and that is incorporated in the GMC filter in the last stage. So that is why the oral linearity of the receiver chain that will be improved and hence the overall performance has been improved in the overall receiver chain.

This is 2 of my achievements right now. I have submitted 2 papers in the three papers basically in the ITP access and one of them in the ITP transition, the nanotechnology and the other one is the IEEE magnetic address.

This is a few of my research publications.

Your research publications clearly underscore your significant contributions to RF microelectronics and receiver front end design. The innovations such as replacing passive inductors with active inductors to optimize chip area and incorporating advanced linearity improvement techniques demonstrate a strong capacity for solving complex problems in the field. Publishing in and submitting to IEEE journals like Transactions on Nanotechnology and others speaks to the impact and recognition of your work within the academic and professional community. Finally, regarding your experience in industry projects or consultancy, could you share any notable examples where you applied your expertise practically?

Sorry to interrupt, we're down to the last 5 minutes.

So I have not worked in industries but in the last semester I have taken 1M tech project. The design of a level shifter.

So they have given the that kiss from the one of the industry, uh.

One of the industry people, so they have shared one of the.

Specification could design the level shifter so they have gone given the specification. I have designed the same thing using TSMC 61 nanopart technology and purchaser 2 by.

Bring the Monte Carlo in the corner masses so that they can be able to.

Maybe it is other applications while designing the check.

Target for the.

65, not 61.

Thank you for clarifying, Professor Yadav. Utilizing TSMC 65nm technology and performing Monte Carlo simulations along with corner analysis showcases your technical proficiency and your readiness to meet real-world application requirements effectively. This concludes the skill verification portion of the interview. Thank you for providing such detailed insights into your expertise and experiences. Is there anything you would like to add or discuss further?

Can I know that how you are basically approaching why you are adding this particular initial round stage into the whole interview process is set for the first time or?

I cannot answer that. Let’s stay focused on this interview. Is there anything else you’d like to address related to your qualifications or expertise?

No, that's all to myself.

Just to confirm, Professor Yadav, would you like to end the interview now? Please let me know explicitly.

So I just want to add, uh, I just want to know that, uh.

What?

Sorry.

Can you please repeat the thing? What?

You just told me.

Uh, right now don't have any questions, so because that is all from my side. So if that is, uh, if the interview will be completed, then we can conclude.

I was asking if there’s anything else you’d like to discuss or share before we conclude the interview. If not, please confirm explicitly if you’d like to end the interview.

Thank you for clarifying. To ensure proper protocol, could you please explicitly confirm if you'd like me to end the interview?

Yes, please end the interview.